// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.4.0.70
// Netlist written on Wed Dec 24 11:23:07 2014
//
// Verilog Description of module ip_gddr71rx
//

module ip_gddr71rx (alignwd, clk_phase, clkin, phasedir, phaseloadreg, 
            phasestep, pll_reset, ready, sclk, sync_clk, sync_reset, 
            datain, q0, q1, q2, q3) /* synthesis syn_noprune=1, NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(215[8:19])
    input alignwd;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(218[16:23])
    output [6:0]clk_phase;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(227[23:32])
    input clkin;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(219[16:21])
    input phasedir;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(220[16:24])
    input phaseloadreg;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(221[16:28])
    input phasestep;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(222[16:25])
    input pll_reset;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(223[16:25])
    output ready;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(228[17:22])
    output sclk;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(229[17:21])
    input sync_clk;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(224[16:24])
    input sync_reset;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(225[16:26])
    input [3:0]datain;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(226[22:28])
    output [6:0]q0;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(230[23:25])
    output [6:0]q1;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(231[23:25])
    output [6:0]q2;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(232[23:25])
    output [6:0]q3;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(233[23:25])
    
    wire sync_clk /* synthesis SET_AS_NETWORK=sync_clk */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(224[16:24])
    wire n903 /* synthesis nomerge= */ ;
    
    wire Inst5_IB3, Inst5_IB2, Inst5_IB1, Inst5_IB0, reset, eclko;
    wire [2:0]cs_gddr_sync;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(79[13:25])
    
    wire start, clkos, clkop, scuba_vlo, eclkfb, Inst8_IB, VCC_net;
    
    IDDR71B Inst6_IDDR71B3 (.D(Inst5_IB3), .SCLK(sclk), .RST(reset), .ECLK(eclko), 
            .ALIGNWD(alignwd), .Q0(q3[0]), .Q1(q3[1]), .Q2(q3[2]), .Q3(q3[3]), 
            .Q4(q3[4]), .Q5(q3[5]), .Q6(q3[6])) /* synthesis syn_instantiated=1 */ ;
    defparam Inst6_IDDR71B3.GSR = "ENABLED";
    IDDR71B Inst6_IDDR71B2 (.D(Inst5_IB2), .SCLK(sclk), .RST(reset), .ECLK(eclko), 
            .ALIGNWD(alignwd), .Q0(q2[0]), .Q1(q2[1]), .Q2(q2[2]), .Q3(q2[3]), 
            .Q4(q2[4]), .Q5(q2[5]), .Q6(q2[6])) /* synthesis syn_instantiated=1 */ ;
    defparam Inst6_IDDR71B2.GSR = "ENABLED";
    IDDR71B Inst6_IDDR71B1 (.D(Inst5_IB1), .SCLK(sclk), .RST(reset), .ECLK(eclko), 
            .ALIGNWD(alignwd), .Q0(q1[0]), .Q1(q1[1]), .Q2(q1[2]), .Q3(q1[3]), 
            .Q4(q1[4]), .Q5(q1[5]), .Q6(q1[6])) /* synthesis syn_instantiated=1 */ ;
    defparam Inst6_IDDR71B1.GSR = "ENABLED";
    IDDR71B Inst6_IDDR71B0 (.D(Inst5_IB0), .SCLK(sclk), .RST(reset), .ECLK(eclko), 
            .ALIGNWD(alignwd), .Q0(q0[0]), .Q1(q0[1]), .Q2(q0[2]), .Q3(q0[3]), 
            .Q4(q0[4]), .Q5(q0[5]), .Q6(q0[6])) /* synthesis syn_instantiated=1 */ ;
    defparam Inst6_IDDR71B0.GSR = "ENABLED";
    IB Inst5_IB3_c (.I(datain[3]), .O(Inst5_IB3)) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(307[8:51])
    ECLKSYNCB Inst3_ECLKSYNCB (.ECLKI(clkos), .STOP(cs_gddr_sync[0]), .ECLKO(eclko)) /* synthesis syn_instantiated=1 */ ;
    ECLKSYNCB Inst2_ECLKSYNCB (.ECLKI(clkop), .STOP(scuba_vlo), .ECLKO(eclkfb)) /* synthesis syn_instantiated=1 */ ;
    VLO scuba_vlo_inst (.Z(scuba_vlo));
    EHXPLLL Inst1_EHXPLLL (.CLKI(Inst8_IB), .CLKFB(eclkfb), .PHASESEL0(scuba_vlo), 
            .PHASESEL1(scuba_vlo), .PHASEDIR(phasedir), .PHASESTEP(phasestep), 
            .PHASELOADREG(phaseloadreg), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
            .RST(pll_reset), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), 
            .ENCLKOS2(scuba_vlo), .ENCLKOS3(scuba_vlo), .CLKOP(clkop), 
            .CLKOS(clkos), .LOCK(start)) /* synthesis FREQUENCY_PIN_CLKOS="378.000000", FREQUENCY_PIN_CLKOP="108.000000", FREQUENCY_PIN_CLKI="108.000000", ICP_CURRENT="11", LPF_RESISTOR="72", syn_instantiated=1 */ ;
    defparam Inst1_EHXPLLL.CLKI_DIV = 1;
    defparam Inst1_EHXPLLL.CLKFB_DIV = 1;
    defparam Inst1_EHXPLLL.CLKOP_DIV = 7;
    defparam Inst1_EHXPLLL.CLKOS_DIV = 2;
    defparam Inst1_EHXPLLL.CLKOS2_DIV = 1;
    defparam Inst1_EHXPLLL.CLKOS3_DIV = 1;
    defparam Inst1_EHXPLLL.CLKOP_ENABLE = "ENABLED";
    defparam Inst1_EHXPLLL.CLKOS_ENABLE = "ENABLED";
    defparam Inst1_EHXPLLL.CLKOS2_ENABLE = "DISABLED";
    defparam Inst1_EHXPLLL.CLKOS3_ENABLE = "DISABLED";
    defparam Inst1_EHXPLLL.CLKOP_CPHASE = 6;
    defparam Inst1_EHXPLLL.CLKOS_CPHASE = 1;
    defparam Inst1_EHXPLLL.CLKOS2_CPHASE = 0;
    defparam Inst1_EHXPLLL.CLKOS3_CPHASE = 0;
    defparam Inst1_EHXPLLL.CLKOP_FPHASE = 0;
    defparam Inst1_EHXPLLL.CLKOS_FPHASE = 0;
    defparam Inst1_EHXPLLL.CLKOS2_FPHASE = 0;
    defparam Inst1_EHXPLLL.CLKOS3_FPHASE = 0;
    defparam Inst1_EHXPLLL.FEEDBK_PATH = "CLKOP";
    defparam Inst1_EHXPLLL.CLKOP_TRIM_POL = "RISING";
    defparam Inst1_EHXPLLL.CLKOP_TRIM_DELAY = 0;
    defparam Inst1_EHXPLLL.CLKOS_TRIM_POL = "RISING";
    defparam Inst1_EHXPLLL.CLKOS_TRIM_DELAY = 0;
    defparam Inst1_EHXPLLL.OUTDIVIDER_MUXA = "DIVA";
    defparam Inst1_EHXPLLL.OUTDIVIDER_MUXB = "DIVB";
    defparam Inst1_EHXPLLL.OUTDIVIDER_MUXC = "DIVC";
    defparam Inst1_EHXPLLL.OUTDIVIDER_MUXD = "DIVD";
    defparam Inst1_EHXPLLL.PLL_LOCK_MODE = 0;
    defparam Inst1_EHXPLLL.PLL_LOCK_DELAY = 200;
    defparam Inst1_EHXPLLL.STDBY_ENABLE = "DISABLED";
    defparam Inst1_EHXPLLL.REFIN_RESET = "DISABLED";
    defparam Inst1_EHXPLLL.SYNC_ENABLE = "DISABLED";
    defparam Inst1_EHXPLLL.INT_LOCK_STICKY = "ENABLED";
    defparam Inst1_EHXPLLL.DPHASE_SOURCE = "ENABLED";
    defparam Inst1_EHXPLLL.PLLRST_ENA = "ENABLED";
    defparam Inst1_EHXPLLL.INTFB_WAKE = "DISABLED";
    IB Inst8_IB_c (.I(clkin), .O(Inst8_IB)) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(284[8:43])
    IDDR71B Inst7_IDDR71B (.D(Inst8_IB), .SCLK(sclk), .RST(reset), .ECLK(eclko), 
            .ALIGNWD(alignwd), .Q0(clk_phase[0]), .Q1(clk_phase[1]), .Q2(clk_phase[2]), 
            .Q3(clk_phase[3]), .Q4(clk_phase[4]), .Q5(clk_phase[5]), .Q6(clk_phase[6])) /* synthesis syn_instantiated=1 */ ;
    defparam Inst7_IDDR71B.GSR = "ENABLED";
    IB Inst5_IB2_c (.I(datain[2]), .O(Inst5_IB2)) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(310[8:51])
    IB Inst5_IB1_c (.I(datain[1]), .O(Inst5_IB1)) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(313[8:51])
    IB Inst5_IB0_c (.I(datain[0]), .O(Inst5_IB0)) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(316[8:51])
    CLKDIVF Inst4_CLKDIVF (.CLKI(eclko), .RST(reset), .ALIGNWD(alignwd), 
            .CDIVX(sclk)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst4_CLKDIVF.GSR = "DISABLED";
    defparam Inst4_CLKDIVF.DIV = "3.5";
    GSR GSR_INST (.GSR(VCC_net));
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    ip_gddr71rxgddr_sync Inst_gddr_sync (.sync_clk(sync_clk), .sync_reset(sync_reset), 
            .stop(cs_gddr_sync[0]), .n903(n903), .ready(ready), .start(start), 
            .reset(reset)) /* synthesis syn_module_defined=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(281[26] 282[70])
    LUT4 m0_lut (.Z(n903)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
    defparam m0_lut.init = 16'h0000;
    VHI i752 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module ip_gddr71rxgddr_sync
//

module ip_gddr71rxgddr_sync (sync_clk, sync_reset, stop, n903, ready, 
            start, reset) /* synthesis syn_module_defined=1 */ ;
    input sync_clk;
    input sync_reset;
    output stop;
    input n903;
    output ready;
    input start;
    output reset;
    
    wire sync_clk /* synthesis SET_AS_NETWORK=sync_clk */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(224[16:24])
    wire n903 /* synthesis nomerge= */ ;
    
    wire n871, reset_flag;
    wire [3:0]ctrl_cnt;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(77[13:21])
    wire [3:0]n15;
    
    wire n96, n110;
    wire [2:0]cs_gddr_sync;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(79[13:25])
    
    wire n179;
    wire [3:0]n171;
    
    wire n140, n116, n716, n872, n874;
    wire [2:0]stop_assert;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(78[13:24])
    
    wire n875;
    wire [2:0]n1;
    
    wire n329, n18, n863, n876, ddr_reset_d, n870, n873, n877, 
        n350, n864, n762, n36, n10, n756, n869;
    
    LUT4 i148_3_lut_4_lut (.A(n871), .B(reset_flag), .C(ctrl_cnt[0]), 
         .D(ctrl_cnt[1]), .Z(n15[1])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A ((C (D)+!C !(D))+!B))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(79[13:25])
    defparam i148_3_lut_4_lut.init = 16'h0ee0;
    PFUMX i278 (.BLUT(n96), .ALUT(n110), .C0(cs_gddr_sync[1]), .Z(n179));
    FD1S3DX reset_flag_65 (.D(n179), .CK(sync_clk), .CD(sync_reset), .Q(reset_flag));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam reset_flag_65.GSR = "ENABLED";
    LUT4 i1_4_lut (.A(n171[3]), .B(reset_flag), .C(n140), .D(n871), 
         .Z(n15[3])) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))) */ ;
    defparam i1_4_lut.init = 16'ha088;
    FD1P3DX cs_gddr_sync_i0 (.D(n716), .SP(n116), .CK(sync_clk), .CD(sync_reset), 
            .Q(stop)) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam cs_gddr_sync_i0.GSR = "ENABLED";
    FD1S3DX ctrl_cnt__i0 (.D(n15[0]), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam ctrl_cnt__i0.GSR = "ENABLED";
    LUT4 i1_3_lut_4_lut (.A(ctrl_cnt[0]), .B(n872), .C(reset_flag), .D(n874), 
         .Z(n110)) /* synthesis lut_function=(A (B (C)+!B (C+(D)))+!A (C)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(270[10:14])
    defparam i1_3_lut_4_lut.init = 16'hf2f0;
    LUT4 i569_2_lut_rep_12 (.A(stop_assert[1]), .B(stop_assert[0]), .Z(n875)) /* synthesis lut_function=(A (B)) */ ;
    defparam i569_2_lut_rep_12.init = 16'h8888;
    LUT4 i573_2_lut_3_lut (.A(stop_assert[1]), .B(stop_assert[0]), .C(stop_assert[2]), 
         .Z(n1[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;
    defparam i573_2_lut_3_lut.init = 16'h7878;
    FD1P3DX ctrl_cnt__i3 (.D(n15[3]), .SP(n329), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam ctrl_cnt__i3.GSR = "ENABLED";
    FD1P3DX ctrl_cnt__i2 (.D(n18), .SP(n329), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam ctrl_cnt__i2.GSR = "ENABLED";
    LUT4 n135_bdd_4_lut (.A(cs_gddr_sync[1]), .B(reset_flag), .C(ctrl_cnt[0]), 
         .D(n872), .Z(n863)) /* synthesis lut_function=(A ((D)+!C)+!A !(B+((D)+!C))) */ ;
    defparam n135_bdd_4_lut.init = 16'haa1a;
    LUT4 i651_2_lut_rep_13 (.A(ctrl_cnt[0]), .B(ctrl_cnt[1]), .Z(n876)) /* synthesis lut_function=(A (B)) */ ;
    defparam i651_2_lut_rep_13.init = 16'h8888;
    FD1S3BX ddr_reset_d_67 (.D(n903), .CK(sync_clk), .PD(sync_reset), 
            .Q(ddr_reset_d)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam ddr_reset_d_67.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_7_3_lut (.A(ctrl_cnt[0]), .B(ctrl_cnt[1]), .C(ctrl_cnt[2]), 
         .Z(n870)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_2_lut_rep_7_3_lut.init = 16'h8080;
    FD1P3DX ctrl_cnt__i1 (.D(n15[1]), .SP(n329), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam ctrl_cnt__i1.GSR = "ENABLED";
    LUT4 i102_2_lut_3_lut_4_lut (.A(ctrl_cnt[0]), .B(ctrl_cnt[1]), .C(ctrl_cnt[3]), 
         .D(ctrl_cnt[2]), .Z(n171[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;
    defparam i102_2_lut_3_lut_4_lut.init = 16'h78f0;
    FD1P3DX stop_assert_64__i1 (.D(n1[1]), .SP(n873), .CK(sync_clk), .CD(sync_reset), 
            .Q(stop_assert[1]));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(123[22:37])
    defparam stop_assert_64__i1.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_14 (.A(stop), .B(cs_gddr_sync[1]), .Z(n877)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_14.init = 16'heeee;
    FD1P3DX cs_gddr_sync_i1 (.D(n864), .SP(n350), .CK(sync_clk), .CD(sync_reset), 
            .Q(cs_gddr_sync[1])) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam cs_gddr_sync_i1.GSR = "ENABLED";
    FD1P3DX stop_assert_64__i0 (.D(n1[0]), .SP(n873), .CK(sync_clk), .CD(sync_reset), 
            .Q(stop_assert[0]));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(123[22:37])
    defparam stop_assert_64__i0.GSR = "ENABLED";
    LUT4 i667_2_lut_3_lut_4_lut (.A(ready), .B(n877), .C(ctrl_cnt[3]), 
         .D(reset_flag), .Z(n329)) /* synthesis lut_function=(!(A (C)+!A (B (C)+!B (C (D))))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(79[13:25])
    defparam i667_2_lut_3_lut_4_lut.init = 16'h0f1f;
    FD1P3DX stop_assert_64__i2 (.D(n1[2]), .SP(n873), .CK(sync_clk), .CD(sync_reset), 
            .Q(stop_assert[2]));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(123[22:37])
    defparam stop_assert_64__i2.GSR = "ENABLED";
    FD1P3DX cs_gddr_sync_i2 (.D(n762), .SP(n350), .CK(sync_clk), .CD(sync_reset), 
            .Q(ready)) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=281, LSE_RLINE=282 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam cs_gddr_sync_i2.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_8_3_lut (.A(stop), .B(cs_gddr_sync[1]), .C(ready), 
         .Z(n871)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_rep_8_3_lut.init = 16'hfefe;
    LUT4 i1_2_lut_3_lut_3_lut (.A(stop), .B(cs_gddr_sync[1]), .C(ready), 
         .Z(n350)) /* synthesis lut_function=(!(A (C)+!A (B))) */ ;
    defparam i1_2_lut_3_lut_3_lut.init = 16'h1b1b;
    LUT4 i664_4_lut (.A(n877), .B(n36), .C(reset_flag), .D(ready), .Z(n18)) /* synthesis lut_function=(!(A (B)+!A (B+!(C+(D))))) */ ;
    defparam i664_4_lut.init = 16'h3332;
    LUT4 i1_2_lut_rep_11 (.A(stop), .B(ready), .Z(n874)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_rep_11.init = 16'h2222;
    LUT4 scuba_vlo_bdd_2_lut_3_lut (.A(stop), .B(ready), .C(n863), .Z(n864)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam scuba_vlo_bdd_2_lut_3_lut.init = 16'h2020;
    LUT4 i146_3_lut_4_lut (.A(n871), .B(reset_flag), .C(ctrl_cnt[0]), 
         .D(ctrl_cnt[3]), .Z(n15[0])) /* synthesis lut_function=(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D)))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(79[13:25])
    defparam i146_3_lut_4_lut.init = 16'he00e;
    LUT4 i2_3_lut_rep_9 (.A(ctrl_cnt[1]), .B(ctrl_cnt[3]), .C(ctrl_cnt[2]), 
         .Z(n872)) /* synthesis lut_function=((B+(C))+!A) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam i2_3_lut_rep_9.init = 16'hfdfd;
    LUT4 i564_1_lut (.A(stop_assert[0]), .Z(n1[0])) /* synthesis lut_function=(!(A)) */ ;
    defparam i564_1_lut.init = 16'h5555;
    LUT4 i2_4_lut (.A(stop), .B(cs_gddr_sync[1]), .C(n10), .D(start), 
         .Z(n762)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam i2_4_lut.init = 16'h1000;
    LUT4 i34_4_lut (.A(ctrl_cnt[3]), .B(n876), .C(ctrl_cnt[2]), .D(n871), 
         .Z(n36)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B (C+(D))+!B !(C))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(79[13:25])
    defparam i34_4_lut.init = 16'hc7c3;
    LUT4 i1_4_lut_adj_1 (.A(ready), .B(ctrl_cnt[3]), .C(reset_flag), .D(n870), 
         .Z(n10)) /* synthesis lut_function=(A+!(B+!(C (D)))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam i1_4_lut_adj_1.init = 16'hbaaa;
    LUT4 reset_flag_bdd_4_lut_736 (.A(reset_flag), .B(n140), .C(n756), 
         .D(stop), .Z(n869)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A (C+(D))) */ ;
    defparam reset_flag_bdd_4_lut_736.init = 16'hddf0;
    LUT4 i670_3_lut (.A(cs_gddr_sync[1]), .B(ready), .C(stop), .Z(n116)) /* synthesis lut_function=(!(A+(B (C)))) */ ;
    defparam i670_3_lut.init = 16'h1515;
    LUT4 i2_3_lut (.A(ready), .B(n869), .C(cs_gddr_sync[1]), .Z(n716)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
    defparam i2_3_lut.init = 16'h0404;
    LUT4 i1_2_lut_4_lut (.A(ctrl_cnt[1]), .B(ctrl_cnt[3]), .C(ctrl_cnt[2]), 
         .D(ctrl_cnt[0]), .Z(n140)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam i1_2_lut_4_lut.init = 16'hfdff;
    LUT4 i566_2_lut (.A(stop_assert[1]), .B(stop_assert[0]), .Z(n1[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i566_2_lut.init = 16'h6666;
    LUT4 i2_3_lut_rep_10 (.A(reset_flag), .B(stop_assert[2]), .C(start), 
         .Z(n873)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam i2_3_lut_rep_10.init = 16'h1010;
    LUT4 i1_4_lut_adj_2 (.A(ready), .B(reset_flag), .C(start), .D(stop), 
         .Z(n96)) /* synthesis lut_function=(A (B (C+(D)))+!A (B)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(270[10:14])
    defparam i1_4_lut_adj_2.init = 16'hccc4;
    LUT4 i2_2_lut_4_lut (.A(reset_flag), .B(stop_assert[2]), .C(start), 
         .D(n875), .Z(n756)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(105[3] 137[6])
    defparam i2_2_lut_4_lut.init = 16'h1000;
    LUT4 i4_2_lut (.A(cs_gddr_sync[1]), .B(ddr_reset_d), .Z(reset)) /* synthesis lut_function=(A+(B)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71rx/ip_gddr71rx.v(89[20:49])
    defparam i4_2_lut.init = 16'heeee;
    
endmodule
